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| +22 dBm PSAT 3V Power Amplifier for 0.5 - 6 GHz Applications Technical Data MGA-83563 Features * +22 dBm PSAT at 2.4 GHz, 3.0 V +23 dBm PSAT at 2.4 GHz, 3.6 V * 22 dB Small Signal Gain at 2.4 GHz * Wide Frequency Range 0.5 to 6 GHz * Single 3 V Supply * 37% Power Added Efficiency * Ultra Miniature Package Surface Mount Package SOT-363 (SC-70) Description Agilent's MGA-83563 is an easyto-use GaAs RFIC amplifier that offers excellent power output and efficiency. This part is targeted for 3V applications where constant-envelope modulation is used. The output of the amplifier is matched internally to 50 . However, an external match can be added for maximum efficiency and power out (PAE = 37%, Po = 22 dBm). The input is easily matched to 50 . Due to the high power output of this device, it is recommended for use under a specific set of operating conditions. The thermal sections of the Applications Information explain this in detail. The circuit uses state-of-the-art PHEMT technology with proven reliability. On-chip bias circuitry allows operation from single supply voltage. Pin Connections and Package Marking Vd1 GND 1 2 3 6 5 4 OUTPUT and Vd2 GND GND 83x Applications * Amplifier for Driver and Output Applications INPUT Note: Package marking provides orientation and identification; "x" is date code. Equivalent Circuit (Simplified) OUTPUT and Vd2 Vd1 INPUT BIAS BIAS GROUND 2 MGA-83563 Absolute Maximum Ratings Symbol V Pin Tch TSTG Parameter Maximum DC Supply Voltage CW RF Input Power Channel Temperature Storage Temperature Units V dBm C C Absolute Maximum[1] 4 +13 165 -65 to 150 Thermal Resistance[2]: ch to c = 175C/W Notes: 1. Operation of this device above any one of these limits may cause permanent damage. 2. TC = 25C (TC is defined to be the temperature at the package pins where contact is made to the circuit board). POWER DISSIPATED AS HEAT (mW) Pd = (VOLTAGE) x (CURRENT) - (Pout) 800 700 600 500 400 300 200 100 0 10 30 50 70 90 110 130 150 1 x CASE TEMPERATURE (C) Temperature/Power Derating Curve. 10 6H rs M TT F 3.0V 20 pF 2.2 nH 18 nH 50 pF 1 pF RF OUTPUT 83 RF 1.2 nH INPUT Figure 1. MGA-83563 Final Production Test Circuit. Vd 20 pF L1 Tuner Bias Tee RF OUTPUT 83 Tuner RF INPUT Circuit A: L1 = 2.2 nH for 0.1 to 3 GHz Circuit B: L1 = 0 nH (capacitor as close as possible) for 3 to 6 GHz Figure 2. MGA-83563 Test Circuit for Characterization. 3 MGA-83563 Electrical Specifications, Vd = 3 V, TC = 25C, using test circuit of Figure 2, unless noted. Symbol PSAT PAE [3] Id[5] Gain Parameters and Test Conditions Saturated Output Power[3] Power Added Efficiency Device Current Small Signal Gain f = 0.9 GHz f = 1.5 GHz f = 2.0 GHz f = 2.4 GHz f = 4.0 GHz f = 5.0 GHz f = 6.0 GHz f = 0.9 GHz f = 1.5 GHz f = 2.0 GHz f = 2.4 GHz f = 4.0 GHz f = 5.0 GHz f = 6.0 GHz f = 0.9 GHz f = 1.5 GHz f = 2.0 GHz f = 2.4 GHz f = 4.0 GHz f = 5.0 GHz f = 6.0 GHz f = 0.9 GHz f = 1.5 GHz f = 2.0 GHz f = 2.4 GHz f = 4.0 GHz f = 5.0 GHz f = 6.0 GHz f = 2.4 GHz f = 2.4 GHz Units dBm % mA dB Min. 20.5 25 Typ. 22.4 37 152 20 22 23 22 22 19 17 20.9 21.7 21.8 22 21.9 19.7 18.2 41 41 40 37 32 18 14 19.1 19.7 19.7 19.2 18.1 16 15 3.5 2.6 2.3 1.4 2.5 3.5 4.5 dB dBm -38 -30 29 200 Max. Std. Dev.[4] 0.75 2.5 12.4 PSAT Saturated Output Power dBm PAE Power Added Efficiency % P1 dB [5] Output Power at 1 dB Gain Compression dBm VSWR in Input VSWR into 50 Circuit A Circuit B f = 0.9 to 1.7 GHz f = 1.8 to 3.0 GHz f = 3.0 to 6.0 GHz f = 0.9 to 2.0 GHz f = 2.0 to 3.0 GHz f = 3.0 to 4.0 GHz f = 4.0 to 6.0 GHz f = 0.9 to 3.0 GHz f = 3.0 to 6.0 GHz f = 0.9 GHz to 6.0 GHz VSWRout Output VSWR into 50 Circuit A Circuit B ISOL IP3 Isolation Third Order Intercept Point Notes: 3. Measured using the final test circuit of Figure 1 with an input power of +4 dBm. 4. Standard Deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. 5. For linear operation, refer to thermal sections in the Applications section of this data sheet. 4 MGA-83563 Typical Performance, Vd = 3 V, TC = 25C, using test circuit of Figure 2, unless noted. 26 24 22 22 22 24 24 GAIN (dB) 20 18 16 14 3.3 V 12 3.0 V 2.7 V 10 0 1 20 PSAT (dBm) 2 3 4 5 6 P1dB (dBm) 20 18 2.7 V 16 3.0 V 3.3 V 3.6 V 14 0 1 18 2.7 V 16 3.0 V 3.3 V 3.6 V 14 0 1 2 3 4 5 6 2 3 4 5 6 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 3. Tuned Gain vs. Frequency and Voltage. Figure 4. Output Power at 1 dB Compression vs. Frequency and Voltage. Figure 5. Saturated Output Power (+4 dBm in) vs. Frequency and Voltage. 26 24 24 12 GAIN (dB) 20 18 16 14 12 10 0 -40C +25C +85C 1 2 3 4 5 6 20 NOISE FIGURE (dB) -40C +25C +85C 0 1 2 3 4 5 6 22 OUTPUT POWER (dBm) 22 10 8 18 6 -40C +25C +85C 0 1 2 3 4 5 6 16 4 14 FREQUENCY (GHz) FREQUENCY (GHz) 2 FREQUENCY (GHz) Figure 6. Gain vs. Frequency and Temperature. Figure 7. Saturated Output Power (+4 dBm in) vs. Frequency and Temperature. Figure 8. Noise Figure vs. Frequency and Temperature. 10 200 180 170 50 Id DEVICE CURRENT, I d (mA) 8 160 140 120 100 80 60 40 20 0 -40C +25C +85C 0 1 2 3 4 DEVICE CURRENT, I d (mA) 150 40 INPUT 4 110 PAE 20 2 OUTPUT 0 0 1 2 3 4 5 6 FREQUENCY (GHz) 90 70 -14 10 0 6 -10 -6 -2 2 FREQUENCY (GHz) INPUT POWER (dBm) @ 2.4 GHz Figure 9. Input and Output VSWR vs. Frequency. Figure 10. Supply Current vs. Voltage and Temperature. Pin = -27 dBm. Figure 11. Device Current and Power Added Efficiency vs. Input Power. Note: Figure 1 test circuit. PAE (%) VSWR 6 130 30 5 MGA-83563 Typical Performance, continued Vd = 3 V, TC = 25C, using test circuit of Figure 2, unless noted. 24 THIRD ORDER INTERCEPT (dBm) OUTPUT POWER (dBm) PAE (%) and IP3 (dBm) 2.7V 3.0V 22 3.3V 3.6V 20 18 16 14 12 10 -10 33 2.7V 32 3.0V 3.3V 31 3.6V 30 29 28 27 26 25 -14 -10 -6 -2 2 6 50 45 40 35 30 25 20 0 1 2 3 4 5 6 -8 -6 -4 -2 0 2 4 6 INPUT POWER (dBm) @ 2.4 GHz INPUT POWER (dBm) @ 2.4 GHz FREQUENCY (GHz) Figure 12. Output Power vs. Input Power and Voltage. Note: Figure 1 test circuit. Figure 13. Third Order Intercept vs. Input Power and Voltage. Note: Figure 1 test circuit. Figure 14. Power Added Efficiency and Third Order Intercept vs. Frequency (Vd = 3.6 V). -20 -25 ISOLATION (dB) -30 -35 -40 -45 -50 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 15. Isolation vs. Frequency. 6 MGA-83563 Test Circuit Typical s-parameters are shown below for various inductor values (L). Those marked "Sim" are simulated and those marked "Meas" are measured using an ICM (Intercontinental Microwave) fixture. Figure 17 shows the available gain for each L value. The user should first select the L value for the application frequency before designing an input, output, or power matching structure. 50 pF L Bias Tee GAIN (dB) 26 24 22 20 18 16 14 12 18 nH 8.2 nH 4.7 nH 2.2 nH 1.2 nH Vd 0 nH 83 IN s-parameter reference plane OUT 10 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 16. S-parameter Test Circuit. Table 1. MGA-83563 Typical Scattering Parameters [1] TC = 25C, Vd = 3.0 V, Id = 165 mA, CW Operation, Pin = -27 dBm L Sim 18.0 nH Sim 18.0 nH Sim 18.0 nH Sim 18.0 nH Sim 18.0 nH Sim 8.2 nH Sim 8.2 nH Sim 8.2 nH Sim 8.2 nH Sim 8.2 nH Sim 8.2 nH Sim 4.7 nH Sim 4.7 nH Sim 4.7 nH Sim 4.7 nH Sim 4.7 nH Meas 2.2 nH Meas 2.2 nH Meas 2.2 nH Meas 2.2 nH Meas 2.2 nH Sim 1.2 nH Sim 1.2 nH Sim 1.2 nH Sim 1.2 nH Sim 1.2 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Meas 0.0 nH Figure 17. Available Gain (Gmax) vs. Frequency for the MGA-83563 Amplifier over Various Inductance Values. Freq. RIin S11 |S21|2 S21 Gain S12 RLout S22 GHz dB Mag Ang Gain Mag Ang dB Mag Ang dB Mag Ang 0.6 0.8 1.0 1.4 1.8 0.8 1.0 1.4 1.8 2.0 2.4 1.4 1.8 2.0 2.4 2.8 1.8 2.0 2.4 2.8 3.0 2.4 2.8 3.0 3.2 3.6 3.0 3.4 3.8 4.0 4.2 4.6 5.0 5.4 5.8 6.0 -4.6 -9.6 -16.0 -10.1 -7.3 -4.1 -5.8 -13.0 -13.0 -10.7 -8.2 -6.7 -12.0 -14.3 -11.9 -9.4 -6.3 -7.4 -7.9 -7.1 -6.6 -7.9 -10.8 -11.9 -12.3 -11.7 -5.6 -4.7 -5.5 -7.4 -8.4 -9.0 -9.2 -9.7 -7.8 -6.6 0.59 0.33 0.16 0.31 0.43 0.63 0.51 0.22 0.22 0.29 0.39 0.46 0.25 0.19 0.26 0.34 0.49 0.43 0.40 0.44 0.47 0.40 0.29 0.25 0.24 0.26 0.53 0.58 0.53 0.43 0.38 0.36 0.35 0.33 0.41 0.47 -48 -57 -27 22 17 -36 -45 -45 13 18 15 -44 -43 -23 10 12 -53 -51 -36 -27 -25 -41 -37 -29 -20 -7 -33 -31 -50 -52 -48 -44 -39 -32 -29 -46 23.9 24.6 24.1 21.7 19.1 21.2 22.7 23.7 22.4 21.3 19.1 22.1 22.9 22.6 21.1 19.1 21.5 21.9 20.9 19.0 18.0 20.5 20.7 20.5 20.0 18.6 17.9 20.1 20.0 19.4 18.7 17.0 15.4 13.8 12.4 12.1 15.61 16.96 16.02 12.22 9.03 11.52 13.65 15.30 13.15 11.65 8.98 12.72 13.99 13.53 11.36 9.03 11.92 12.48 11.07 8.93 7.90 10.61 10.90 10.56 9.97 8.49 7.87 10.13 9.95 9.28 8.62 7.08 5.87 4.88 4.16 4.03 43 6 -25 -68 -97 48 22 -27 -68 -84 -111 4 -37 -57 -90 -115 -23 -45 -82 -113 -123 -36 -67 -82 -95 -120 -13 -43 -81 -94 -106 -129 -145 -159 -170 177 -46.7 -39.0 -35.5 -32.8 -31.7 -47.4 -41.1 -33.7 -30.9 -30.3 -29.5 -37.6 -32.3 -30.8 -29.2 -28.3 -37.2 -34.8 -32.4 -31.2 -31.0 -33.4 -30.4 -29.4 -28.6 -27.5 -39.1 -34.1 -31.7 -30.9 -30.2 -28.8 -27.9 -27.2 -25.9 -24.9 0.005 0.011 0.017 0.023 0.026 0.004 0.009 0.021 0.029 0.031 0.034 0.013 0.024 0.029 0.035 0.038 0.014 0.018 0.024 0.027 0.028 0.021 0.030 0.034 0.037 0.042 0.011 0.020 0.026 0.028 0.031 0.036 0.040 0.044 0.051 0.057 105 102 87 66 54 95 111 94 74 67 57 109 94 85 70 61 90 85 68 56 52 97 88 82 76 67 109 107 94 93 91 84 78 77 73 64 -21.1 -16.8 -10.1 -5.8 -4.4 -17.2 -35.2 -10.4 -5.5 -4.4 -3.4 -26.7 -9.9 -7.1 -4.3 -3.2 -15.1 -9.7 -6.2 -4.1 -4.1 -18.0 -9.6 -7.4 -5.9 -4.1 -12.8 -7.9 -6.2 -4.5 -3.5 -3.1 -3.0 -3.0 -3.6 -3.3 0.09 0.15 0.31 0.51 0.61 0.14 0.02 0.30 0.53 0.60 0.68 0.05 0.32 0.44 0.61 0.69 0.18 0.33 0.49 0.63 0.62 0.13 0.33 0.43 0.51 0.62 0.23 0.40 0.49 0.60 0.67 0.70 0.71 0.71 0.66 0.68 150 -130 -146 177 150 121 130 -139 -179 166 141 -78 -143 -164 163 138 -100 -130 -175 150 138 -120 -168 176 161 137 -7 -73 -132 -148 -163 173 155 140 127 123 K 4.47 2.37 1.80 1.48 1.45 6.01 3.13 1.54 1.21 1.16 1.14 2.44 1.44 1.26 1.09 1.05 2.40 1.82 1.52 1.40 1.48 1.98 1.47 1.34 1.24 1.14 4.07 1.72 1.43 1.38 1.27 1.25 1.29 1.38 1.47 1.33 Gmax dB 25.8 25.2 24.6 23.5 22.0 23.5 24.0 24.3 24.1 23.7 22.5 23.1 23.7 23.7 23.4 22.5 22.8 23.3 22.8 22.1 21.1 21.3 21.6 21.6 21.5 21.0 19.6 22.7 22.6 22.1 21.9 20.5 19.0 17.3 15.7 15.9 Note: 1. Reference plane per Figure 26 in Applications Information section. 7 MGA-83563 Applications Information The MGA-83563 is two-stage, medium power GaAs RFIC amplifier designed to be used for driver and output stages in transmitter applications operating within the 500 MHz to 6 GHz frequency range. This device is designed for operation in the saturated mode where it delivers a typical output power of +22 dBm (158 mW) with a power-added efficiency of 37%. The MGA-83563 has a large signal gain of 18 dB requiring an input signal level of only +4 dBm to drive it well into saturation. The high output power and high efficiency of the MGA-83563, combined with +3-volt operation and subminiature packaging, make this device especially useful for battery-powered, personal communication applications such as wireless data, cellular phones, and PCS. The upper end of the frequency range of the MGA-83563 extends to 6 GHz making it a useful solution for medium power amplifiers in wireless communications products such as 5.7 GHz spread spectrum or other ISM/ license-free band applications. Internal capacitors on the RFIC chip limit the low-end frequency response to applications above approximately 500 MHz. The thermal limitations of the subminiature SOT-363 (SC-70) package generally restrict the use of the MGA-83563 to applications that use constant envelope types of modulation. These types of systems are able to take full advantage of the MGA-83563's high efficiency, saturated mode of operation. The use of the MGA-83563 for linear applications at reduced power levels is discussed in the "Thermal Design for Reliability" and "Use of the MGA-83563 for Linear Applications" in this applications note. L2 1 RFC 6 3 RF Input Vd RF Input Application Guidelines The use of the MGA-83563 is very straightforward. The on-chip, partial RF impedance matching and integrated bias control circuit simplify the task of using this device. The design steps consist of (1) selecting an interstage inductor from the data provided, (2) adding provision for bringing in the DC bias, and (3) designing and optimizing an output impedance match for the particular frequency band of interest. The input is already well matched to 50 ohms for most frequencies and in many cases no additional input matching will be necessary. Each of the three design steps for using the MGA-83563 will now be discussed in greater detail. Figure 18. Interstage Inductor L2 and Bias Current. The values for inductor L2 are somewhat dependent on the specific printed circuit board material, thickness, and RF layout that are used. The inductor values shown in Figure 19 have been created for the PCB and RF layout that is used for the circuit examples presented in this application note. The methodology that was used to determine the optimum values for L2 and for creating Figure 19 is presented in the Appendix. If the user's PCB and/or layout differ significantly from the example circuits, refer to the Appendix for a description of how to determine the values of L2 for any arbitrary frequency, PCB material, or RF layout. Step 1 -- Selecting the Interstage Inductor The drain of the first stage FET of this two-stage RFIC amplifier is connected to package Pin 1. The supply voltage Vd is connected to this drain through an inductor, L2, as shown in Figure 18. The supply end of the inductor is bypassed to ground. This interstage inductor serves the purpose of completing the impedance match between the first and second stages. The value of inductor L2 depends on the particular frequency for which the MGA-83563 is to be used and is chosen from the look-up graph in Figure 19. Step 2 -- Bias Connections The MGA-83563 is a voltagebiased device and operates from a single, positive power supply. The supply voltage, typically +3-volts, must be applied to the drains of both stages of the RFIC amplifier. The connection to the first stage drain is made through the interstage inductor, L2, as described in the previous step. The supply voltage is applied to the second stage drain through Pin 6, which is also the RF Output connection. Referring to Figure 18, an inductor (RFC) is used to separate the RF output signal from the DC supply. The 8 40 30 20 L2 (nH) 10 9 8 7 6 5 4 3 2 The starting place is to design a circuit that matches the small signal ml (the reflection coefficient of the load impedance required to conjugately match the output of the MGA-83563) to 50 ohms. The small signal S-parameter data for designing the output circuit is taken from Table 1, using the data corresponding to be nearest value of interstage inductor that was chosen in step one. A RF CAD program such as Agilent's Touchstone can be used to easily calculate ml. Touchstone will interpolate the Table 1 S-parameter data for the particular design frequency of interest. As the MGA-83563 is driven into saturation, the output impedance will generally become lower. Choose a circuit topology that will match ml as well as the range of impedances on the low side of ml. Beginning with this small signal output match, tune the circuit under large signal conditions for maximum saturated output power and best efficiency. It should be noted that both the saturated output power (Psat) and power-added efficiency (PAE) for each MGA-83563 is 100% RF tested at 2.4 GHz in a production test fixture that simulates an actual amplifier application. This method of testing not only guarantees minimum performance standards, but also ensures repeatable RF performance in the user's production circuits. 1 0.9 0.8 0.7 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) Figure 19. Values for Interstage Inductor L2. supply side of the RFC is capacitively bypassed. A DC blocking capacitor is used at the output to isolate the supply voltage from the succeeding stage. In order to prevent loss of output power, the value of the RFC is chosen such that its reactance is several hundred ohms at the frequency band of operation. At higher frequencies, it may be practical to use a length of high impedance transmission line (preferably /4) in place of the RFC. The value of the DC blocking and RF bypass capacitors are chosen to provide a small reactance (typically < 1) at the lowest operating frequency. Since both stages of the RFIC are biased from the same voltage source, particular care should be taken to ensure that the supply line between the two is well bypassed to prevent inadvertent feedback from the RF output to the drain of the first stage. Otherwise, the circuit could become unstable. The RF Input (Pin 3) connection to the MGA-83563 is at DC ground potential. The use of a DC blocking capacitor at the input of the MGA-83563 is not required unless a circuit that has a DC voltage present at its output precedes the RFIC. Although at ground potential, the input to the MGA-83563 should not be used as a current sink. Step 3 -- Output Impedance Match The most interesting aspect of using the MGA-83563 is arriving at an optimum, large signal impedance match at the output. A simple but effective approach is to begin with a circuit that provides a small signal impedance match, then empirically adjust the tuning for optimum large signal performance. 9 Step 4 (Optional) -- Input Impedance Match As previously noted, the internal input impedance match to the MGA-83563 is already reasonably good (return loss is typically 8 dB) and may be adequate for many applications as is. The design of the MGA-83563 is such that the second stage will enter into compression before the first stage. The isolation provided by the first stage therefore results in a minimal impact on the input matching as the amplifier becomes saturated. If an improved input return loss is needed, an input circuit is designed to match 50 to ms (the reflection coefficient of the source impedance for a conjugate match at the input of the MGA-83563). The value of ms is calculated from the S-parameters in Table 1 in the same way as was done for ml. Since the real part of the input impedance to the MMIC is near 50 and the reactive part is capacitive, the addition of a simple series inductor is often all that is needed if a better input match is required. Figure 21. Basic PCB Layout. PCB Materials FR-4 or G-10 printed circuit board type of material is a good choice for most low cost wireless applications for frequencies through 3 GHz. Typical singlelayer board thickness is 0.020 to 0.031 inches. Multi-layer boards generally use a dielectric layer thickness in the 0.005 to 0.010 inch range. For higher frequency applications, e.g., 5.8 GHz, circuit boards made with PTFE/glass dielectric materials are suggested. 0.026 This layout is a microstripline design (solid groundplane on the backside of the circuit board) with a 50 input and output and provision for inductor L2 with its bypass capacitor. Adequate RF grounding is critical to obtain maximum performance and to maintain device stability. All of the ground pins of the RFIC should be connected to the RF groundplane on the backside of the PCB by means of plated through holes (vias) that are placed very near the package terminals. As a minimum, one via should be located next to each ground pin to ensure good RF grounding. It is a good practice to use multiple vias as in Figure 21 to further minimize ground path inductance. While it might be considered an effective RF practice, it is recommended that the PCB pads for the ground pins not be connected together underneath the body of the package for two reasons. The first reason is that connecting the ground pins of multi-stage amplifiers together can sometimes result in undesirable feedback between stages. Each ground pin should have its own independent path to ground. The second reason is that PCB traces hidden under the package cannot be adequately inspected for solder quality. 0.075 PCB Layout Recommendations When laying out a printed circuit board for the MGA-83563, several points should be taken into account. The PCB layout will be a balance of electrical, thermal, and assembly considerations. 0.035 0.016 Figure 20. PCB Pad Layout for MGA-83563 Package (dimensions in inches). Package Footprint A recommended printed circuit board footprint for the miniature SOT-363 (SC-70) package that is used by the MGA-83563 is shown in Figure 20. RF Considerations Starting with the package padprint of Figure 20, the nucleus of a PCB layout is shown in Figure 21. This layout is a good general purpose starting point for designs using the MGA-83563 amplifier. 83 This package footprint provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the high frequency performance of the MGA-83563. (The padprint in Figure 20 is shown with the footprint of a SOT-363 package superimposed on the PCB pads for reference.) Vd1 Bypass Capacitor RF Input L2 RF Output 10 Thermal Considerations The DC power dissipation of the MGA-83563, which can be on the order of 0.5 watt, is approaching the thermal limits of subminiature packaging such as the SOT-363. As a result, particular care should be taken to adequately heatsink the MGA-83563. The primary heat path from the MMIC chip to the system heatsink is by means of conduction through the package leads and ground vias to the groundplane on the backside of the PCB. As previously mentioned in the "PCB Layout" section, the use of multiple vias near all of the ground pins is desirable for low inductance. The use of multiple vias is also an especially important part of the heatsinking function. For heatsinking purposes, a thinner PCB with more vias, thicker clad metal, and heavier plating in the vias all result in lower thermal resistance and better heat conduction. Circuit boards thicker than 0.031 inches are not recommended for both thermal and electrical reasons. The importance of good thermal design on reliability is discussed in the next section. The following examples show the thermal prerequisites for using the MGA-83563 reliably in both saturated and linear modes. From Figure 22, Pin + PDC = Pout + Pdiss where Pin and Pout are the RF input and output power, PDC is the DC input power, and Pdiss is the power dissipated as heat. For the saturated mode, Pout = Psat , and, Pdiss = Pin + PDC - Psat From the table of Electrical Specifications, the device current (typical) is 152 mA with a power supply voltage of 3 volts. Referring to Figure 10, it can be seen that the current will decrease approximately 8% at elevated temperatures. The device DC power consumption is then: PDC = 3.0 volts * 152 mA * 0.92 PDC = 420 mW For a saturated amplifier, the RF input power level is +4 dBm (2.51 mW) and the saturated output power is +22 dBm (158 mW). The power dissipated as heat is then: Pdiss = 2.51 + 420 - 158 mW Pdiss = 264 mW The channel-to-case thermal resistance ( ch-c) from the table of Absolute Maximum Ratings is 175C/watt. Note that the meaning of "case" for packages such as the SOT-363 is defined as the interface between the package pins and the mounting surface, i.e., at the PCB pads. The temperature rise from the mounting surface to the MMIC channel is then calculated as 0.264 watt * 175C/watt, or 46C. Saturated Mode Thermal Example Less heat is dissipated in the MGA-83563 when operated in the saturated mode because a significant amount of power is removed from the RFIC as RF signal power. It is for this reason that the saturated mode allows the device to be used reliably at higher circuit board temperatures than for full power, linear applications. As an illustration of a thermal/ reliability calculation, consider the case of an MGA-83563 biased at 3.0 volts for use in a saturated mode application with a MTTF reliability goal of 106 hours (114 years). Reliability calculations will first be presented for nominal conditions, followed by the conservative approach of using worst-case conditions. The first step is to calculate the power dissipated by the MGA-86353 as heat. Power flow for the MGA-83563 is represented in Figure 22. PDC Thermal Design for Reliability Good thermal design is an important consideration in the reliable use of medium power devices such as the MGA-83563 because the Mean Time To Failure (MTTF) of semiconductor devices is inversely proportional to the operating temperature. Pin Pn = 0 HEAT Pdiss Pout Figure 22. Thermal Representation of MGA-83563. 11 Operating life tests [1] for the MGA-83563 have established that a MTTF of 106 hours will be met for channel temperatures 150C. To achieve the 106 hour MTTF goal, the circuit to which the device is mounted (i.e., the case temperature) should therefore not exceed 150 - 46C, or 104C. Repeating the reliability calculation using the worst case maximum device current of 200 mA, the DC power dissipation is 552 mW. Summing the RF input and output powers, Pdiss is 397 mW which results in a channel-to-case temperature rise of 69C. The maximum case temperature for the MTTF goal of 106 hours is then 150- 69C, or 81C. For other MTTF goals, power dissipation, or operating temperatures, Agilent publishes reliability data sheets based on operating life tests to enable designers to arrive at a thermal design for their particular operating environment. For a reliability data sheet covering the MGA-83563, request Agilent publication number 59644128E, titled "GaAs MMIC Amplifier Reliability Data." This reliability data sheet covers the Agilent family of PHEMT GaAs RFICs. The maximum power dissipation for reliable linear operation is calculated in the same manner as was done for the saturated amplifier example. For linear circuits, the RF input and output power are negligible and assumed to be zero. All of the DC power is thus dissipated as heat. For purposes of comparison to the saturated mode example, this calculation will use the same MTTF goal of 106 hours and supply voltage of 3 volts. Calculations are again made for both nominal and worst case conditions. From the data of Figure 10, the typical 3-volt, small signal device current for the MGA-83563 at elevated temperatures is 156 mA. The total device power dissipation, Pdiss, is then 3.0 volts * 156 mA, or 468 mW. The temperature increment from the RFIC channel to case is 0.468 watt * 175C/watt, or 82C. Commensurate with the MTTF goal of 106 hours, the circuit to which the device is mounted should therefore not exceed 150- 82C, or 68C. For the worst case calculation, a guard band of 40% is added to the typical current to arrive at a maximum DC current of 218 mA. The Pdiss is 655 mW and the channel-to-case temperature rise is 115C. The maximum case temperature for worst case current condition is 35C. A case temperature of 68C for nominal operation, or 35C in the worst case, is unacceptably low for most applications. In order to use the MGA-83562 reliably for linear applications, the Pdiss must be lowered by reducing the supply voltage. The implication on RF output power performance for amplifiers operating with a reduced Vd is covered later in this application note in the section subtitled "Use of the MGA-83563 for Linear Applications". Design Example for 2.5 GHz The design of a 2.5 GHz amplifier will be used to illustrate the approach for using the MGA-83563. The basic design procedure outlined earlier will be used, in which the interstage inductor (L2) is chosen first, followed by the design of an initial small signal, output match. The output match will then be empirically optimized for large signal conditions after which an input match will be added. The printed circuit layout in Figure 21 is used as the starting place. The circuit is designed for fabrication on 0.031-inch thick FR-4 dielectric material. Interstage Inductor L2 The first step is to choose a value for the interstage inductor, L2. Referring to Figure 19, a value of 1.5 nH corresponds to the design frequency of 2.5 GHz. A chip inductor is chosen for L2 in this example. However, for small inductance values such as this, the interstage inductor could also be realized with a length of high impedance transmission line. The interstage inductor is bypassed with a 62 pF capacitor, which has a reactance of 1 at 2.5 GHz. Connecting the supply voltage to the bypassed side of the inductor completes the interstage part of the amplifier. Linear Amplifier Thermal Example If the MGA-83563 is used in a linear application, the total power dissipation is significantly higher than for the saturated mode. The dissipated power is greater due to higher device current (not as efficient as the saturated mode) and also because no signal power is being removed. 12 Output Match The design of the small signal output matching circuit begins with the calculation of the small signal match impedance, ml. The set of S-parameters in Table 1 for an inductor value of 1.2 nH is used since this is the closest value to the 1.5 nH that was chosen for L2 in the first design step. Agilent's Touchstone program was used to interpolate the sparameter data and calculate a ml of 0.14 172 for 2.5 GHz. This ml point is plotted on the Smith chart in Figure 23 as Point C, along with an indication of the area of lower impedance from this point. (The output impedance is expected to decrease under large signal conditions.) A two-element matching network consisting of a shunt capacitor and series transmission line is chosen to match the output to 50 ohms. 1 0.5 C (ml) 0.2 B A (50 ) 2 (For the latter reason, impedance matching circuits using series capacitors are avoided.) In some cases, it may be more practical to implement the series transmission line element with a chip inductor. If the series line is excessively long, the cost of an additional chip component can be traded off against circuit board space. The substitution of an open-circuit line for the shunt C may also be possible, thus eliminating the a capacitor. Referring to the Smith chart in Figure 23, the initial output match for ml was determined to be a 0.4 pF shunt capacitor followed by a 0.32-inch length of 50 microstripline. amplifier's output. An ammeter is used to observe total device DC current drain (I d) as an indication of amplifier efficiency. The desired output match is then achieved at the tuning point of maximum Psat and minimum I d. The optimum output match for 2.5 GHz was achieved with a shunt capacitor value of 0.9 pF located 0.08 inches along the 50 line from the output pin of the MGA-83563. The final output circuit is shown in Figure 24. RF Input RF Output MGA83563 50 0.08 in. 0.9 pF Figure 24. Final RF Output Match for the 2.5 GHz Amplifier Tuned for Maximum Psat. DC Bias A 22 nH RFC is added to the 50 side of the output matching circuit to apply bias voltage to the drain of the second stage. The RFC is bypassed with a 62 pF capacitor. A series DC blocking capacitor, also 62 pF, is added to the RF output to complete the bias circuit. When tuned for maximum saturated output power, the small signal output return loss for the amplifier was measured as 5.5 dB at 2.5 GHz. Input Match The input return loss without any external matching was measured as 7.6 dB (2.4:1 VWSR). For many applications no further matching is necessary. If, however, an improved input match is required, a simple series inductor is all that will be needed. Agilent's Touchstone CAD program is again used to extrapolate the 2.5 GHz S-parameters in Table 1 and calculate a small signal ms of 0.37 47. The conjugate of ms, 0.37 -47, is plotted on the Smith chart as Point A in Figure 25. RF Output MLIN C 1A C 2 Optimizing the Output Match To reach the final output matching circuit for maximum saturated output power, an input power of +4 dBm is applied to saturate the amplifier circuit. The output matching circuit is then experimentally optimized by adjusting the value of the shunt capacitor and the distance the capacitor is located along the output line from the MGA-83563. During the tuning process, the saturated output power of the amplifier is monitored with a power meter connected to the LARGE SIGNAL B -0.2 -0.5 -1 -2 Figure 23. Initial Output Match for Small Signal. The shunt-C, series-line topology is chosen based on its ability to cover the expected range of impedance to be matched and because it will pass DC bias into the output pin of the MGA-83563. 13 1 0.5 C (50 ) 0.2 B A (ms*) 2 RF Input 2.7 nH 50 0.17 in. MGA83563 RF Output 28 26 24 GAIN (dB) RF Input 0.2 0.5 L1 MLIN 1 C 2 A Figure 26. Final Large Signal RF Input Match for the 2.5 GHz Amplifier. 22 20 18 16 14 2 2.2 2.4 2.6 2.8 3 FREQUENCY (GHz) -0.2 B -0.5 -1 -2 The addition of the 2.7 nH series inductor increased the large signal input return loss from 7.6 dB (with no matching) to 14.8 dB (1.4:1 VSWR) at 2.5 GHz. Figure 25. Initial Small Signal Input Match. Completed 2.5 GHz Amplifier A schematic diagram of the final 2.5 GHz circuit is shown in Figure 27. All unmarked capacitors are 62 pF. Vd L1 = 2.7 nH RF Input 50 0.17 in 3 L2 = 1.5 nH 1 6 50 0.08 in RFC = 22 nH Figure 29. Small Signal Gain of the Completed 2.5 GHz Amplifier. Figure 27. Schematic Diagram of 2.5 GHz Amplifier. RETURN LOSS (dB) The completed 2.5 GHz amplifier assembly with all components is shown in Figure 28. +3V Input Figure 28. Completed 2.5 GHz Amplifier Assembly. The small signal gain of the completed amplifier was measured as 22.0 dB at 2.5 GHz. Gain over a frequency range of 2.0 to 3.0 GHz is shown in Figure 29. 83 L1 83 The addition of a 0.15 inch length (actual length on FR-4) of 50 transmission line rotates Point A around to Point B on the R = 1 circle of the Smith chart. A series 2.5 nH inductor (L1) is then all that is required to complete the match to 50 at Point C. While the input impedance of the MGA-83563 is somewhat isolated from the nonlinear effects of the saturated output stage, some empirical optimization of the input inductor may increase the input return loss still further. The input is easily fine-tuned under large signal conditions by observing the input return loss while an input power of +4 dBm is applied to the amplifier. The input inductor is then "swept" by placing various values of chip inductors across the gap provided in the 50 line at the input of the MGA-83563. For this example amplifier, increasing the inductor from the initial small signal value of 2.5 nH to 2.7 nH was found to provide the best input match. The final input circuit tuned as for large signal conditions is shown in Figure 26. The (small signal) input and output return losses for the completed amplifier are 14.9 dB and 5.5 dB respectively at 2.5 GHz. Input and output return loss over the 2.0 to 3.0 GHz frequency range is shown in Figure 30. 0 OUTPUT RF Output C2 = 0.9 pF -5 -10 -15 INPUT -20 -25 2 2.2 2.4 2.6 2.8 3 FREQUENCY (GHz) C L2 C RFC C2 C Output Figure 30. Input and Output Return Loss of the Completed 2.5 GHz Amplifier. Table 2 summarizes measured results for this particular amplifier at 2.5 GHz. Output Gain Power Id (dB) (dBm) (mA) 22.0 21.0 17.8 -- 19.2 21.8 148 165 139 Mode Small Signal G-1dB Saturated Table 2. Performance Summary for 2.5 GHz Amplifier. 14 The power-added efficiency (PAE) in the saturated mode is 36% as calculated from: PRF PAE = PDC PAE = (Pout - Pin) PDC The length of the series line between the output of the MGA-83563 and C2 is also part of the matching circuit. This line was not considered as a variable in the sensitivity analysis since photofabrication of micro-striplines on circuit boards is highly repeatable. Psat and PAE for each value of C2 are plotted in Figure 32. Inspection of Figure 32 reveals that a variation in C2 of 10% is acceptable for most applications. 25 Note the current increases slightly from small signal conditions to the 1 dB compression point, then falls appreciably as the amplifier goes into saturation. (The 1-dB compressed output power will be higher for amplifiers that are tuned for linear performance.) The most important observation of this data is that the PAE remains high for values of C2 that are toward the left of the maximum Psat point (lower values of C2), while the PAE begins to drop off toward for higher values of C2. This data points out the importance of choosing a value for C2 that is toward the lower side of the maximum Psat point (lower C2) in order to maintain high efficiency with production tolerance components. 40% Psat 20 35% Psat (dBm) The output match of the completed 2.5 GHz amplifier was held fixed while various values of L2 were substituted for the purposes of (1) verifying the optimum value for L2, and (2) determining the sensitivity of Psat and PAE to the value of L2. These results are plotted in Figure 31. The data in Figure 31 indicates there is some tradeoff between tuning for maximum output power and maximum efficiency. The original choice of 1.5 nH for the interstage inductor L2 appears well optimized. PAE 10 25% 20% 5 15% 0 0 0.5 1 1.5 2 L2 (nH) 2.5 3 3.5 4 10% Figure 31. 2.5 GHz Psat and PAE vs. L2. 23 22.5 22 21.5 21 50% 45% Psat 40% Psat (dBm) The results of this tuning process supplied the 2.5 GHz data point referred to in the Appendix that was used to create Plot B of Figure 47. 35% PAE 20.5 20 19.5 30% 25% Output Match Sensitivity The sensitivity of Psat and PAE to the value of the shunt capacitor in the output matching circuit was investigated by varying the value of C2 while noting Psat and device current. The input power was fixed at +4 dBm for this test. 19 18.5 18 0 0.5 1 C2 (pF) 1.5 2 20% 15% 10% Figure 32. 2.5 GHz Psat and PAE vs. C2. PAE (%) PAE (%) Psat and PAE Sensitivity to Inductor L2 30% 15 15 Amplifier Designs for 1.9 GHz and 900 MHz The same design process used for the 2.5 GHz amplifier above was repeated for the design of amplifiers for the 1.9 GHz and 900 MHz frequency bands. Example circuits were built using the same PCB layout as used for the 2.5 GHz amplifier. The schematic diagram, component values, and assembly drawing for the 1.9 GHz and 900 MHz designs are shown in the "Summary of Example Amplifiers" section. 1.9 GHz Amplifier Measured Results Performance of this amplifier is summarized in Table 3. The PAE is 41%. Output Gain Power Id (dB) (dBm) (mA) 23.8 22.8 17.5 -- 19.6 21.5 155 182 114 The small signal input and output return loss over the 1.5 to 2.3 GHz frequency range is shown in Figure 34. 0 OUTPUT Gain over the 500 to 1300 MHz frequency range is shown in Figure 35. 26 24 -4 RETURN LOSS (dB) 22 -8 GAIN (dB) INPUT 20 18 16 14 0.5 -12 -16 -20 1.5 0.7 0.9 1.1 1.3 1.7 1.9 2.1 2.3 FREQUENCY (GHz) FREQUENCY (GHz) Figure 34. Input and Output Return Loss of the 1.9 GHz Amplifier. Figure 35. Small Signal Gain of the 900 MHz Amplifier. Mode Small Signal G-1dB Saturated Mode Small Signal G-1dB Saturated Output Gain Power Id (dB) (dBm) (mA) 24.5 23.5 18.5 -- 20.9 22.5 168 177 144 RETURN LOSS (dB) 900 MHz Amplifier Measured Results Measured results for this 900 MHz amplifier is shown in Table 4. The PAE is 40%. Input and output return loss (small signal) from 500 to 1300 MHz is shown in Figure 36. 0 OUTPUT -5 -10 INPUT -15 Table 3. Performance Summary for 1.9 GHz Amplifier. Small signal gain over the 1.5 to 2.3 GHz frequency range is shown in Figure 33. -20 0.5 0.7 0.9 1.1 1.3 Table 4. Performance Summary for 900 MHz Amplifier. FREQUENCY (GHz) Figure 36. Input and Output Return Loss of the 900 MHz Amplifier. 26 24 22 GAIN (dB) 20 18 16 14 1.5 1.7 1.9 2.1 2.3 FREQUENCY (GHz) Figure 33. Small Signal Gain of the Completed 1.9 GHz Amplifier. 16 Psat and PAE Sensitivity to Inductor L2 for the 900 MHz Amplifier As was done for the 2.5 GHz amplifier example, values for L2 were "swept" for verification and to observe sensitivity of Psat and PAE. The results are plotted in Figure 37. This process verified the correct value of L2 and provided the 900 MHz data point used in the Appendix to create Plot B of Figure 47. 23.0 22.8 22.6 22.4 Psat (dBm) Summary of Example Amplifiers A schematic diagram for the three example amplifiers covering 2.5 GHz, 1.9 GHz, and 900 MHz is shown in Figure 38. Component values for the three designs are summarized in Table 5. (nH, pF) L1 L2 L3 L4 C2 C1, C3, C4 C5 Frequency 900 MHz 1.9 GHz 2.5 GHz 5.6 12 82 3.6 150 2.2 2.7 33 1.2 82 1000 2.7 1.5 22 0.9 62 Not used (short circuit) Table 5. Component Values for Example Amplifiers. 55% 50% The completed amplifier with all components and SMA connectors is shown in Figure 39. The circuit is fabricated on 0.031-inch FR-4 material. The additional 1000 pF bypass capacitor, C5, was added to the bias line near the Vd connection to eliminate interstage feedback. This layout has provision for an inductor (L4) at the output of the MGA-83563. This inductor is not used in for these example amplifiers and is replaced by a short. Psat 45% 22.2 22.0 21.8 40% PAE 21.6 21.4 21.2 21.0 0 5 10 15 20 25 L2 (nH) 30 35 40 45 30% 35% Figure 37. 900 MHz Psat and PAE vs. L2. C1 Vd C4 L1 RF Input 50 0.17 in 3 1 L2 C5 L3 (RFC) RF Output L4 50 0.08 in C2 C3 4 6 Figure 38. Schematic Diagram for the Example Amplifiers. PAE (%) 83 17 +Vd C5 Operation at Higher Supply Voltages While the MGA-83563 is designed primarily for use in +3 volt applications, the output power can be increased by using a higher supply voltage. Referring to Figure 5, the Psat can be increased by up to 1 dB by using a power supply voltage of +3.6 volts. Note: If bias voltages greater than 3 volts are used, appropriate caution should be given to both the thermal limits and the Absolute Maximum Ratings. L2 IN L1 L3 83 C4 C2 C3 L4 OUT MGA-83-A Figure 39. Completed MGA-83563 Amplifier Assembly. Use of the MGA-83563 for Linear Applications Due to the thermal limitations covered in the "Thermal Design for Reliability" section, the MGA83563 is best suited for use as a saturated mode amplifier. The MGA-83563 can however be used with reduced output power performance by lowering the supply voltage. Some saturated amplifier applications may also benefit from operation at reduced Vd for the purpose of reducing current drain and extending battery life. P1dB and Psat vs. Vd for the 2.5 GHz and 900 MHz circuit examples are shown in Figures 40 and 41, respectively. The methods presented in the "Thermal Design for Reliability" section may be used to arrive at a maximum supply voltage that corresponds to the desired MTTF goal. The P1dB power plotted in Figures 40 and 41 is taken from the example amplifiers tuned for maximum Psat. P1dB will be higher with linear tuning. When designing for linear applications, the value for the interstage inductor L2 is taken from Plot A of Figure 47 in the Appendix. The data in Tables 2- 4 shows that some increase in device current occurs as the output power approaches P1dB. Allowance should be made in the thermal analysis for the increased Pdiss if the circuit is to be used at or near P1dB. 25.00 23.00 21.00 Hints and Troubleshooting Oscillation Unconditional stability of the MGA-83563 is dependent on having good grounding. Inadequate device grounding or poor PCB layout techniques could cause the device to be potentially unstable. In a multistage RFIC such as the MGA-83563, feedback through bias lines supplying voltage to both stages can lead to oscillation. It is important to well bypass the connections to bias supply to ensure stable operation. OUTPUT POWER (dBm) 19.00 17.00 15.00 13.00 11.00 9.00 7.00 5.00 1.00 1.25 Psat P1dB 1.50 1.75 2.00 2.25 2.50 2.70 3.00 3.30 3.50 SUPPLY VOLTAGE, Vd (V) Figure 40. Output Power vs. Supply Voltage for the 2.5 GHz Amplifier. 18 26.00 24.00 OUTPUT POWER (dBm) 22.00 Psat 20.00 18.00 P1dB 16.00 14.00 12.00 1.5 Standard statistics tables or calculations provide the probability of a parameter falling between any two values, usually symmetrically located about the mean. Referring to Figure 42 for example, the probability of a parameter being between 1 is 68.3%; between 2 is 95.4%; and between 3 is 99.7%. 2.0 2.5 SUPPLY VOLTAGE, Vd (V) 3.0 3.5 68% Figure 41. Output Power vs. Supply Voltage for the 900 MHz Amplifier. 95% 99% Statistical Parameters Several categories of parameters appear within this data sheet. Parameters may be described with values that are either "minimum or maximum," "typical," or "standard deviations." The values for parameters are based on comprehensive product characterization data, in which automated measurements are made on of a minimum of 500 parts taken from three nonconsecutive process lots of semiconductor wafers. The data derived from product characterization tends to be normally distributed, e.g., fits the standard bell curve. Parameters considered to be the most important to system performance are bounded by minimum or maximum values. For the MGA-83563, these parameters are: Saturated Output Power (Psat), Power Added Efficiency (PAE), and Device Current (Id). Each of the guaranteed parameters is 100% tested as part of the manufacturing process. Values for most of the parameters in the table of Electrical Specifications that are described by typical data are the mathematical mean (), of the normal distribution taken from the characterization data. For parameters where measurements or mathematical averaging may not be practical, such as S-parameters or Noise Parameters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. Typical values are intended to be used as a basis for electrical design. To assist designers in optimizing not only the immediate amplifier circuit using the MGA-83563, but to also evaluate and optimize trade-offs that affect a complete wireless system, the standard deviation () is provided for many of the Electrical Specifications parameters (at 25C) in addition to the mean. The standard deviation is a measure of the variability about the mean. It will be recalled that a normal distribution is completely described by the mean and standard deviation. -3 -2 -1 Mean () +1 +2 (typical) Parameter Value +3 Figure 42. Normal Distribution. Phase Reference Planes The positions of the reference planes used to specify S-parameters and Noise Parameters for the MGA-83563 are shown in Figure 43. As seen in the illustration, the reference planes are located at the point where the package leads contact the test circuit. REFERENCE PLANES TEST CIRCUIT Figure 43. Phase Reference Planes. SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase 19 reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-363 package, will reach solder reflow temperatures faster than those with a greater mass. The MGA-83563 is qualified to the time-temperature profile shown in Figure 44. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cooldown zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 235C. These parameters are typical for a surface mount assembly process for the MGA-83563. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. (which readily accumulate on the human body and on test equipment) can discharge without detection and may result in degradation in performance, reliability, or failure. Electronic devices may be subjected to ESD damage in any of the following areas: * * * * Storage & handling Inspection & testing Assembly In-circuit use Electrostatic Sensitivity RFICs are electrostatic discharge (ESD) sensitive devices. Although the MGA-83563 is robust in design, permanent damage may occur to these devices if they are subjected to high-energy electrostatic discharges. Electrostatic charges as high as several thousand volts The MGA-83563 is a ESD Class 1 device and proper ESD precautions are recommended when handling, inspecting, testing, assembling, and using these devices to avoid damage. For cases is which the MGA-83563 is used as an output stage with coupling to an external antenna, the device should be protected from high voltage spike damage due to human contact with the antenna. Appendix -- Determination of Interstage Inductor Value. A methodology is presented here for determining the value of the interstage inductor, L2 that produces optimum large signal performance at any frequency. This is the method used to create the plot of Optimum L2 vs. Frequency in Figure 19. This procedure is included as a reference for PCB designs that may differ considerably from the example circuit of Figure 40. 250 TMAX 200 TEMPERATURE (C) 150 Reflow Zone 100 Preheat Zone 50 0 0 60 120 180 240 300 TIME (seconds) Cool Down Zone While the method described here covers a wide range of frequencies for generic applications, the same approach can be used for a Figure 44. Surface Mount Assembly Profile. 20 single frequency of interest. Although the printed circuit board layout of Figure 40 is used here for demonstration purposes, the same procedure is equally applicable to the any other circuit board material, thickness, or topology. This is a 2-step process in which the value for L2 for best small signal performance is first ascertained followed by an empirical adjustment of L2 to allow for large signal effects. The first step in this process is to assemble a test circuit for the MGA-83563 with 50-ohm input and output lines. This test circuit should use the same printed circuit board material, thickness, and ground via arrangement for the MGA-83563 that will be used to the final amplifier circuit. The connection to Pin 1 should have provision for a chip inductor that is bypassed to ground. The bypassed side of the inductor is connected to the supply voltage. The supply voltage is also connected to the RF Output/Vd2 (Pin 6) by means of an external, wideband bias tee. The test circuit is shown in Figure 45. which the maximum gain occurs recorded. Note that the small signal input and output match provided by the internal matching of the MGA-83563 is sufficiently close to 50 ohms for most combinations of L2 and frequencies that further matching would not significantly skew the data. This is a small signal test and the input power level should be less than -15 dBm. 25 taken in a relatively parasiticsterile characterization fixture and computer simulations. The test data in Figure 46 includes the effects of all circuit parasitics, ground vias, parasitics of the actual chip inductor that will be used, and also takes into account the length of line and bypass capacitor used to make the connection to L2 that will be used in the final circuit. The value of L2 is then plotted vs. the frequency at which the gain peak occurred for each value of inductance. This plot is done as a log plot with a straight-line curve fit added to smooth the data. This data, shown as Plot A in Figure 47, then gives the optimum value of L2 for maximum small signal gain, i.e., linear performance. The results of the 2.5 GHz and 900 MHz example amplifiers presented in this Application Note were used to modify Plot A for large signal use. The optimum, large signal value for L2 at 2.5 GHz was determined to be 1.5 nH, and 12 nH for 900 MHz. These two L2-frequency points are added to the data plot of Figure 47. A straight line is drawn through these two points to create Plot B. Plot B provides a look-up for values of L2 for saturated amplifier designs. Plot A is used for linear amplifiers. Note: Plot B is replicated as Figure 19 in the "Application Guidelines" section of this note. 20 GAIN (dB) 15 0 nH 10 1.5 5 15 33 0 0.5 1.0 2.0 3.0 4.7 2.7 6.8 4.0 5.0 6.0 FREQUENCY (GHz) Figure 46. Small Signal Gain vs. Frequency for Various Values of L2. Test Circuit L2 IN 50 50 MGA83563 BIAS TEE +Vd OUT Various values of Toko, Inc.(c) type LL1608 inductors were used for this particular example. An inductance value of 0.5 nH was used for the case of a short circuit placed across the gap provided for L2. For use at 5.8 GHz, Pin 1 should be bypassed through the most direct path (minimum inductance) to ground. Referring to Figure 21, L2 is not used and a bypass capacitor is placed from Pin 1 directly to the ground pad for Pin 2. The result of this step is the multiple plot shown in Figure 46 of gain vs. frequency with L2 as a parameter. This plot is similar to the plot in Table 1, but differs in that the data in Figure 46 is specific to the designer's particular PCB layout. The Table 1 data is a combination of test data Figure 45. L2 Test Circuit. Next, the wideband gain response of the test circuit is observed while substituting various values of chip inductors for L2. For each value of L2, the gain should be plotted and/or the frequency at Operating life test conducted for a case temperature of 60C and with a Vd of 3.6 volts. After 1000 hours, there were 0 failures. [1] 21 40 30 20 L2 (nH) 10 9 8 7 6 5 4 3 2 PLOT A PLOT B 1 0.9 0.8 0.7 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) Figure 47. Optimum L2 for Small Signal Gain vs. Frequency. 22 Package Dimensions Outline 63 (SOT-363/SC-70) PACKAGE MARKING CODE (XX) 1.30 (0.051) REF. DATE CODE (X) 2.20 (0.087) 2.00 (0.079) XXX 1.35 (0.053) 1.15 (0.045) 0.650 BSC (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.425 (0.017) TYP. 0.30 REF. 1.00 (0.039) 0.80 (0.031) 0.25 (0.010) 0.15 (0.006) 10 0.30 (0.012) 0.10 (0.004) 0.20 (0.008) 0.10 (0.004) DIMENSIONS ARE IN MILLIMETERS (INCHES) MGA-83563 Part Number Ordering Information Part Number MGA-83563-TR1 MGA-83563-BLK Devices per Container 3000 100 Container 7" reel Antistatic bag 23 Device Orientation REEL TOP VIEW 4 mm END VIEW CARRIER TAPE USER FEED DIRECTION COVER TAPE 8 mm 83x 83x 83x 83x Tape Dimensions and Product Orientation For Outline 63 P P0 D P2 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 8 MAX. K0 5 MAX. A0 B0 DESCRIPTION CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER DIAMETER PITCH POSITION WIDTH THICKNESS WIDTH TAPE THICKNESS CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) SYMBOL A0 B0 K0 P D1 D P0 E W t1 C Tt F P2 SIZE (mm) 2.24 0.10 2.34 0.10 1.22 0.10 4.00 0.10 1.00 + 0.25 1.55 0.05 4.00 0.10 1.75 0.10 8.00 0.30 0.255 0.013 5.4 0.10 0.062 0.001 3.50 0.05 2.00 0.05 SIZE (INCHES) 0.088 0.004 0.092 0.004 0.048 0.004 0.157 0.004 0.039 + 0.010 0.061 0.002 0.157 0.004 0.069 0.004 0.315 0.012 0.010 0.0005 0.205 0.004 0.0025 0.00004 0.138 0.002 0.079 0.002 PERFORATION CARRIER TAPE COVER TAPE DISTANCE www.semiconductor.agilent.com Data subject to change. Copyright (c) 1999 Agilent Technologies Obsoletes 5966-1730E 5968-6307E (11/99) |
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